1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a synchronous semiconductor memory device which takes in external signals including an address signal and input data in synchronization with an external clock signal, and externally sends storage data. More particularly, the invention relates to a semiconductor memory device having an internal synchronous signal generating circuit such as a PLL (Phase Locked Loop) circuit or a DLL (Delay Locked Loop) circuit which receives an external clock signal and issues a synchronized internal clock signal.
2. Description of the Background Art
In accordance with recent improvement in an operation speed of microprocessors (which will be referred to as "MPUs" hereinafter), it has been proposed to use synchronous DRAMs, which will be referred as "SDRAMs" hereinafter, and operate in synchronization with clock signals in order to achieve fast access of, e.g., dynamic random access memories (which will be referred to as "DRAMs" hereinafter) used as main storage units.
Generally, the semiconductor memory device which operates in synchronization with an external clock signal is internally provided with a PLL circuit, a DLL circuit or the like for generating an internal clock signal in synchronization with the external clock signal.
FIG. 41 is a schematic block diagram showing a structure of a synchronous semiconductor memory device 2000 in the prior art.
An external clock signal Ext.CLK applied to a control signal input terminal 2 is sent to an internal synchronous signal generating circuit 50 via a clock buffer circuit 20. Internal synchronous signal generating circuit 50 issues an internal clock signal int.CLK synchronized with external clock signal Ext.CLK. An internal control signal generating circuit 26 receives internal clock signal int.CLK and issues internal control signals for controlling operations of internal circuitry.
Synchronous semiconductor memory device 2000 further includes an RAS buffer 22 and a CAS buffer 24, which receive external control signals /RAS and /CAS through external control signal input terminals 4 and 6 and issue an internal row address strobe signal and an internal column address strobe signal controlling operations of the internal circuits, respectively, a memory cell array 10 having memory cells arranged in a matrix form, an address buffer 18 which receives external address signals A0-A1 applied via an address signal input terminal 8, and is controlled by RAS and CAS buffers 22 and 24 to issue an internal row address signal and an internal column address signal, a row decoder 12 which decodes an internal row address signal sent from address buffer 18, and selects a corresponding row (word line) in memory cell array 10, a column decoder 14 which is controlled by the internal control signal sent from internal control signal generating circuit 26 to decode the internal column address signal sent from address buffer 18, and thereby issues a column select signal for simultaneously selecting a plurality of corresponding columns in memory cell array 10, a plurality of sense amplifiers which are controlled by the internal control signal sent from internal control signal generating circuit 26 to sense and amplify data of the plurality of memory cells in memory cell array 10 connected to the selected row, an I/O circuit which is controlled by internal control signal generating circuit 26, and connects a plurality of selected columns in memory cell array 10 to an internal data bus in response to a column select signal sent from column decoder 14, a selector circuit 28 which is controlled by internal control signal generating circuit 26 to select and issue data among the data of memory cells issued to the internal data bus, and in particular data corresponding to an internal select address applied from address buffer 18, and an output circuit 30 which is controlled by internal control signal generating circuit 26 to receive an output of selector circuit 28 and issue external output data to data I/O terminal 32.
In the following description, the sense amplifiers and I/O circuit will be collectively called as a sense amplifier+I/O circuit 16.
FIG. 42 is a timing chart showing an operation of the conventional synchronous semiconductor memory device 2000 shown in FIG. 41.
The following description will be given on an operation after a steady state, in which internal clock signal int.CLK synchronized with external clock signal Ext.CLK is issued, is attained after power-on and subsequent start of a synchronizing operation of an internal synchronous signal generating circuit 50.
In response to a rising edge of external clock signal Ext.CLK at time t1, address buffer 18 takes in a row address signal Ax applied through external control signal input terminal 8. In response to this row address signal Ax, row decoder 12 changes a potential on a word line selected in memory cell array 10 to "H" level. In response to this, and particularly in accordance with storage information in the memory cells connected to the selected word line, the sense amplifiers arranged for the bit line pairs connected to these memory cells amplify the potential differences appearing on the bit line pairs.
After the potential levels on bit line pairs are amplified to a full scale, address buffer 18 takes in a column address Ay through external address signal input terminal 8 at time t6, i.e., at a rising edge in a fourth cycle of external clock signal Ext.CLK after time t1. In response to this, a plurality of (e.g., four) bit line pairs corresponding to column address signal Ay are connected to I/O line pairs, and the potential levels on bit line pairs are transmitted onto the I/O line pairs.
The storage data read onto the I/O line pairs is sent to selector 28 through the internal data bus. In accordance with the internal control signal sent from internal control signal generating circuit 26, selector 28 selects data sent from the memory cell, which corresponds to the internal selector address sent from address buffer 18, and sends the same to output circuit 30. Output circuit 30 operates in accordance with the internal control signal sent from internal control signal generating circuit 26, and more specifically sends the latched read data to data I/O terminal 32 at a rising edge of external clock signal Ext.CLK at time t8, i.e., at a rising edge in a second cycle of external clock signal Ext.CLK after taking-in of the column address signal into address buffer 18.
Thus, all the operations, i.e., taking-in of the address signal, reading of data and writing of data in the synchronous semiconductor memory device 2000 are controlled by the internal control signals which are issued from internal control signal generating circuit 26 in accordance with internal clock signal int.CLK issued from internal synchronous signal generating circuit 50. In particular, the timing of data output is synchronized with external clock signal Ext.CLK, and data issued to data I/O terminal 32 is supplied, as read data, into an external device such as an MPU at a falling edge of external clock signal Ext.CLK.
The description has been given on an example, in which four cycles of the external clock signal are required between taking-in of the row address and subsequent taking-in of the column address, and two cycles of the external clock signal are required between taking-in of the column address and subsequent data output. However, these numbers of cycles depend on a frequency of the external clock signal, an operation speed of the internal circuitry of synchronous semiconductor memory device 2000 and others.
FIG. 43 is a circuit diagram showing a structure of the PLL circuit of the conventional internal synchronous signal generating circuit 50.
Referring to FIG. 43, a power supply node 51a is supplied with a power supply potential Vcc, and a ground potential node 51b is supplied with a ground potential GND. A phase comparing circuit 52 receives internal clock signal int.CLK and external clock signal Ext.CLK, and issues control signals UP and /DOWN corresponding to shifts or differences in frequency and phase between internal and external clock signals int.CLK and Ext.CLK.
Phase comparing circuit 52 sets control signal UP to "L" level, when internal clock signal int.CLK is larger in frequency than external clock signal Ext.CLK, or when the phase of internal clock signal int.CLK leads that of external clock signal Ext.CLK. Also, phase comparing circuit 52 sets control signal UP to "H" level, when internal clock signal int.CLK is smaller in frequency than external clock signal Ext.CLK, or when the phase of internal clock signal int.CLK lags behind that of external clock signal Ext.CLK.
Further, phase comparing circuit 52 sets control signal /DOWN to "L" level, when internal clock signal int.CLK is larger in frequency than external clock signal Ext.CLK, or when the phase of internal clock signal int.CLK leads that of external clock signal Ext.CLK. Phase comparing circuit 52 sets control signal /DOWN to "H" level, when internal clock signal int.CLK is smaller in frequency than external clock signal Ext.CLK, or when the phase of internal clock signal int.CLK lags behind that of external clock signal Ext.CLK.
A charge pump circuit 53 receives control signals UP and /DOWN from phase comparing circuit 52, and supplies electric charges to a charge/discharge node 53a when both control signals UP and /DOWN are at "L" level. When control signals UP and /DOWN are at "H" levels, charge pump circuit 53 removes electric charges from charge/discharge node 53a.
Charge pump circuit 53 includes a constant current circuit 53c for flowing a constant current between power supply potential node 51a and a node 53b, a p-channel MOS transistor 53d which is connected between node 53b and charge/discharge node 53a, and receives, on its gate, control signal UP sent from phase comparing circuit 52, an n-channel MOS transistor 53f which is connected between charge/discharge node 53a and a node 53e, and receives, on its gate, control signal /DOWN from phase comparing circuit 52, and a constant current circuit 53g for flowing a constant current between node 53e and ground potential node 51b.
A loop filter 54 supplied an output potential Vp to node 54a in response to supply or removal of charges to or from charge/discharge node 53a in charge pump circuit 53.
Loop filter 54 includes a resistor element 54b connected between charge/discharge node 53a and a node 54a, a resistor element 54d connected between nodes 54a and 54c, and a capacitor 54e connected between node 54c and ground potential node 51b.
A current regulating potential output circuit 55 receives output potential Vp from node 54a in loop filter 54, and issues an output potential Vn corresponding to output potential Vp. Current regulating potential output circuit 55 includes a p-channel MOS transistor 55b which is connected between power supply potential node 51a and a node 55a, and has a gate connected to node 54a in loop filter 54, and an n-channel MOS transistor 55c which is connected between node 55a and ground potential node 51b, and has a gate connected to node 55a.
A ring oscillator 56 receives output potential Vp sent from refresh 54 and output potential Vn sent from current regulating potential output circuit 55, and regulates a frequency of internal clock signal int.CLK oscillating in accordance with a value of a drive current, which is regulated in accordance with output potentials Vp and Vn. Ring oscillator 56 includes odd inverters 56a connected in a ring form. Each inverter 56a includes a current regulating p-channel MOS transistor 56ab, which is connected between power supply potential node 51a and a node 56aa, and receives, on its gate, output potential Vp from loop filter 54, a p-channel MOS transistor 56ac, which is connected between node 56aa and an output node 56ac, and has a gate connected to an input node 56ad, an n-channel MOS transistor 56ag, which is connected between output node 56ac and a node 56af, and has a gate connected to input node 56ad, and a current regulating n-channel MOS transistor 56ah, which is connected between node 56af and ground node 51b, and receives, on its gate, output potential Vn from current regulating potential output circuit 55.
An operation of PLL circuit 50 will be briefly described below.
When the frequency of internal clock signal int.CLK is larger than that of external clock signal Ext.CLK, or the phase of internal clock signal int.CLK leads that of external clock signal Ext.CLK, phase comparing circuit 52 sets control signals UP and /DOWN to "L" level. In charge pump circuit 53 receiving control signals UP and /DOWN, p-channel MOS transistor 53d is turned on, and n-channel MOS transistor 53f is turned off. In response to this, charges are supplied to charge/discharge node 53a, so that output potential Vp on node 54a in loop filter 54 rises. This results in reduction in value of a current flowing through p-channel MOS transistor 55b in current regulating potential output circuit 55 which receives this output potential Vp, and output potential Vn on node 55a lowers. Output potential Vn attains a steady value when the current flowing through n-channel MOS transistor 55c becomes equal in level to the current flowing through p-channel MOS transistor 55b.
In response to lowering of output potential Vn caused by rising of output potential Vp, currents flowing through p- and n-channel MOS transistors 56ab and 56ah for current regulation decrease in each inverter 56a of ring oscillator 56. In response to this, a delay time of each inverter 56a increases. This results in reduction in frequency of internal clock signal int.CLK issued from ring oscillator 56. This reduction in frequency of internal clock signal int.CLK delays rising of internal clock signal int.CLK at a next cycle, so that the led phase varies toward a synchronized phase.
When the frequency of internal clock signal int.CLK is smaller than that of external clock signal Ext.CLK, or the phase of internal clock signal int.CLK lags behind that of external clock signal Ext.CLK, phase comparing circuit 52 issues control signals UP and /DOWN at "H" level. Thereafter, operations are performed in a manner opposite to the above, and the delayed phase of internal clock signal int.CLK issued from ring oscillator 56 changes toward a synchronized phase.
In this manner, PLL circuit 50 issues internal clock signal int.CLK having the same frequency and phase as external clock signal Ext.CLK.
As described before, the oscillation frequency of ring oscillator 56 largely depends on a value of current flowing through each inverter 56a. Thus, the oscillation frequency rises with this current value. However, in ring oscillator 56 of the PLL circuit 50 having the above structure, the drive current of the ring oscillator does not change in proportion to output potential Vp of loop filter 54.
This is because the value of current flowing through each inverter is determined by applying output potential Vp of loop filter circuit 54 to the gate of p-channel MOS transistor 55b. Thus, the value of current flowing through inverter circuit 56a is pursuant to a gate voltage dependency of the drain current flowing through p-channel MOS transistor 55b, and, to be exact, this dependency is not linear with respect to the gate voltage, so that a linear relationship is not established between the output potential of charge pump circuit 53, i.e., output potential Vp of loop filter circuit 54 and a current flowing through inverter 56a forming the ring oscillator.
Therefore, in such a state that PLL circuit 50 is to be synchronized with external clock signal Ext.CLK having an excessively large frequency, i.e., that the output of charge pump circuit 53 is near power supply potential Vcc and the drain current flowing through p-channel MOS transistor 55b is large, or in such a state that the output level of charge pump circuit 53 is near ground potential GND and the drain current flowing through p-channel MOS transistor 55b is small, a relationship between the output of charge pump 53, i.e., output potential Vp of loop filter circuit 54 and the drain current flowing through p-channel MOS transistor 55b deviates significantly from a linear relationship.
Depending on a frequency region of external clock signal Ext.CLK, oscillated internal clock signal int.CLK may vibrate significantly at frequencies slightly larger and smaller than that of external clock signal Ext.CLK, so that jitter of internal clock signal int.CLK may increase.
In addition to the above cause, the jitter may occur due to a value of a constant current supplied from charge pump circuit 53.
FIG. 44 shows a time dependency of the frequency of the signal issued from ring oscillator circuit 56 in the cases where the constant current supplied from charge pump circuit 53 is larger and smaller than a predetermined value. When the constant current supplied from charge pump circuit 53 is large, loop filter 54 is driven by a current of a large value. This reduces a time required for completion of synchronization of PLL circuit 50 with external clock signal Ext.CLK. After the synchronization, however, a large change occurs in the value of current which is supplied from charge pump circuit 53 in accordance with the control signal sent from phase comparing circuit 52, so that the output frequency varies to a large extent after completion of the synchronization, and large jitter occurs.
Conversely, when the constant current supplied from charge pump circuit 53 is small, the frequency does not vary to a large extent after completion of synchronization, but a long time is required until the synchronization is completed.
This means that, in synchronous semiconductor memory device 2000, synchronous signal generating circuit 50 must continue the synchronized operation without interruption in order to issue internal clock signal int.CLK synchronized with external clock signal Ext.CLK. Otherwise, synchronous semiconductor memory device 2000 cannot follow external clock signal Ext.CLK in the data input/output operation. Therefore, the continuous operation of synchronous signal generating circuit 50 is required, which unpreferably increases a power consumption of synchronous semiconductor memory device 2000 during standby.